Hardware Accelerated Motion Estimation
Accelerating Block Matching by 8000x
Members: Chris Francis*, Praveen Venkatesh*, Nishikant Parmar*, Prankush Agarwal Prof Joycee Mekie
Deemed best course project for Digital Systems, 2019 @ IITGN
Designed a motion estimation processor that estimates the motion of objects between two adjacent frames in a video. Implemented the Full Search Block Matching algorithm for processing and a VGA controller for displaying the results. Utilized an asynchronous handshake based finite state machine for implementing the algorithm on a NEXYS 4 DDR FPGA.
Results
- Achieved 8000x improvement in speed compared to a python script running on an Intel i5-8250u. This system forms a fundamental block in several video compression methods.
- I learnt that Verilog isn’t something I want to do for the rest of my life XD.
